This invention relates to a floating-point multiplier device for use in primarily calculating a product of first and second numbers, each comprising an exponent and a mantissa. More particularly, this invention relates to a floating-point multiplier device which is of the type described and for which each mantissa is a normalized mantissa.
It is known to subject the mantissa of such a product to normalization and round off. In the manner which will become clear as the description proceeds, the normalization is to make every mantissa represent a number which is in a predetermined range. It is specified by the IEEE Standard 754 (IEEE Standard for Binary Floating-point Arithmetic, ANSI/IEEE Std. 754-1985) that the predetermined range is between decimal one, inclusive, and decimal two, exclusive. The round off will presently be described.
The first and the second numbers are represented by binary data signals. The first number comprises a first exponent and a first mantissa. The second number comprises a second exponent and a second mantissa. The binary data signals comprise first and second exponent signals representative of the first and the second exponents and first and second mantissa signals representative of the first and the second mantissas. Inasmuch as the first and the second exponent signals and the first and the second mantissa signals are components of the binary data signals, it is possible to understand that each of the first and the second exponent signals consists of a first predetermined numer e of bits. Each of the first and the second mantissa signals is composed of a second predetermined number n of bits.
In the manner which will later be described more in detail, a conventional floating-point multiplier device comprises an exponent adder supplied with the first and the second exponent signals to produce an exponent sum signal representative of an exponent sum of the first and the second exponents. When each of the first and the second numbers is represented by using the exponent which includes a bias value, the exponent sum is given by a three-term sum of the first and the second exponents plus the bias value.
Supplied with the first and the second mantissa signals, a multiplier array produces a carry save sum signal representative of a carry save sum as a provisional product of the first and the second mantissas. In practice, the carry save sum signal consists of a mantissa carry signal representative of mantissa carries and a mantissa sum signal representative of mantissa sums. In any event, the provisional product is represented by a multiplicity of bits which are equal in number to four times the second predetermined number.
Connected to the multiplier array, a mantissa carry propagate adder uses the provisional product in calculating a mantissa product of the first and the second mantissas and produces a mantissa product signal representative of the mantissa product. More particularly, the carry propagate adder calculates a sum of the mantissa carries and the mantissa sums with carry propagation to provide the mantissa product. The mantissa product signal consists of a plurality of bits which are equal in number to twice the second predetermined number.
According to the above-referencee IEEE Standard 754, each mantissa signal comprises an integer bit representative of binary one. The mantissa product signal therefore comprises either a binary zero bit or a binary one bit at its ten's place, namely, as its most significant bit (MSB). The mantissa product signal is subjected to the normalization in compliance with the most significant bit. Broadly speaking, the mantissa product signal is subjected to a one bit rightward shift, namely, one-bit shifted towards its least significant bit (LSB), when the most significant bit is the binary one bit. When the most significant bit is the binary zero bit, the mantissa product signal is subjected to no bit shift, namely, is used as it stands.
In general, a floating-point multiplier device produces an ultimate product signal which represents an ultimate product of the first and the second numbers and which comprises an ultimate exponent signal representative of an ultimate exponent of the ultimate product by the first predetermined number of bits and a rounded-off mantissa signal representative of a rounded-off mantissa of the ultimate product by the second predetermined number of bits. In order to provide the rounded-off mantissa, the mantissa product of an unlimited precision is subjected to round off. More specifically, the mantissa product signal is subjected to round down and round up by dropping decimal bits to the right of (n-1) decimals with the final remaining bit untouched and with one added to the final remaining bit if a binary zero bit and a binary one bit follows the final remaining bit.
In the conventional floating-point multiplier device, an upper-bit selector is for subjecting upper bits of the mantissa product signal to the normalization by subjecting the upper bits to the one-bit rightward shift and to no bit shift when the most significant bit is the binary one and the binary zero bits, respectively. The upper-bit selector thereby produces a normalised product signal representative of a normalized product.
A round off decoder is connected to the mantissa carry propagate adder through a lower-bit selector to judge from lower bits whether the matissa product signal should be subjected to the round down or to the round up. The round off decoder thereby produces a round down and a round up control signal indicative of the round down and the round up.
An ultimate carry propagate adder is connected to the exponent adder through an exponent selector, to the upper-bit selector, and to the round off decoder. The ultimate carry propagate adder is for concatenating the exponent sum signal and the normalized product signal into a concatention and for subjecting the concatenation to the round down and the round up in compliance with the round down and the round up control signals. The ultimate carry propagate adder thereby produces the ultimate product signal.
It should be noted in connection with the conventional floating-pont multiplier device that carry propagate addition is twice carried out until production of the ultimate product signal, first by the mantissa carry propagate adder and subsequently by the ultimate carry propagate adder. When the first and the second numbers are represented by a double precision floating-point representation which is specified by the IEEE Standard 754, the first and the second predetermined numbers are equal to eleven and fifty-three. Incidentally, the bias value is equal to 1023. It is now understood that the conventional floating-point multiplier device must twice carry out the carry propagate addition in which carries are propagated through a long bit length. The conventional floating-point multiplier device therefore requires a long calculation time.